Hardware assist system and method for the timing of packets in a wireless network

ABSTRACT

In an example embodiment, a system for assisting the timing calculation associated with the transmission timing of packets or data frames. The system utilizes the baseband PHY processor to detect the trailing edge of the radio frequency (“RF”) packet and prevents transmission for a pre-determined amount of time after the packet has been received.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application No. 10/192,949 filed on Jul. 11, 2002, the entirety of which is incorporated herein.

BACKGROUND

The use of wireless networks has increased dramatically. WLANs are now commonplace in the modern workplace and becoming more prevalent in many universities and households in the United States. A WLAN offers several advantages over regular local area networks (“LANs”). For example, users are not confined to specified locations previously wired for network access, wireless work stations are relatively easy to link with an existing LAN without the expense of additional cabling or technical support; and WLANs provide excellent alternatives for mobile or temporary working environments.

In general operation, when a mobile terminal or a portable unit is powered up, it “associates” with an access point through which the mobile terminal can maintain wireless communication with the network. In order to associate, the mobile terminal must be within the cell range of the access point and the access point must likewise be situated within the effective range of the mobile terminal. Upon association, the mobile unit is effectively linked to the entire LAN via the access point. As the location of the mobile terminal changes, the access point with which the mobile terminal was originally associated may fall outside the range of the mobile terminal.

Many packets that are received require a response, such as an acknowledgement (ACK) sent within a defined time period. In meeting the responsibilities set forth above, a significant portion of the MAC processing time is spent determining the proper time to send an acknowledgement (“ACK”) signal. In an 802.11a environment, the MAC sends an acknowledgement (“ACK”) signal within a short inter frame space (“SIFS”) of 16 μs after receiving the packet.

One problem is that the MAC does not have any knowledge of the received signal envelope, since the symbol decoding process takes some variable amount of time, the MAC processor typically has to respond to the incoming packet in a very short amount of time with accurate timing, for example within a SIFS in an 802.11 compatible network. Currently, there is a fixed timing reference point in the packet to determine timing. In many cases, this fixed timing reference will be generated before any packet data is transferred. A timing reference may be difficult to detect while the MAC processor is busy receiving packet data. However, given this timing reference at the beginning of the packet, it is still quite difficult to determine the end of the packet or data frame. The total time of the packet must be calculated using a complex algorithm, and an adjustment must be applied based on the knowledge of the relationship between the beginning of the packet and the timing reference signal. Given the decoding delay of the received data, this calculation must be performed in a very short amount of time.

For example, the length calculation for an 802.11a packet is TXTIME=T _(PREAMBLE) +T _(SIGNAL) +T _(SYM)*Ceiling((16+8*LENGTH+6)/N _(DBPS)) Where the TXTIME is the entire time for the transmitting the sum of the following variables: the packet preamble (T_(PREAMBLE)), the time to transmit the signal field (T_(SIGNAL)), and the time to transmit the data portion of the packet (T_(SYM)*Ceiling((16+8*LENGTH+6)/N_(DBPS))), where T_(SYM) is the symbol time in microseconds, LENGTH is the packet length in bytes, and N_(DBPS) is the number of bits per symbol. This is an extremely complex calculation to do in real time and takes a significant amount of processor cycles to accomplish. This is not a desirable solution because of the computational complexity involved and the number of MAC processor cycles required to attend to basic synchronization functions.

Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of instrumentalities and combinations particularly pointed out in the appended claims.

OVERVIEW OF EXAMPLE EMBODIMENTS

In an example embodiment, there is disclosed herein an apparatus, comprising a receiver operable to receive a wireless signal, a transmitter operable to transmit a wireless signal, a detection circuit operable to detect when receiving of the wireless signal is completed coupled to the receiver, and a delay circuit configured to receive a signal to operate the transmitter and a signal from the detection circuit indicative of when receiving of the wireless signal is completed, the delay circuit comprises an output coupled to the transmitter. The delay circuit is responsive to the signal from the detection circuit to delay passing the signal to operate the transmitter to the output coupled to the transmitter after a predetermined time delay.

In an example embodiment disclosed herein is a method comprising receiving a signal and determining when receiving of the signal is completed. The method further comprises generating a response to the signal and delaying the sending of the response a predetermined time period from when receiving of the signal is completed.

In an example embodiment, disclosed herein is an apparatus comprising a wireless transmitter, a wireless receiver, a physical layer (PHY) processor coupled to the receiver and responsive to receive a first data packet from the wireless receiver, the PHY is also coupled to the transmitter and operable to send a second data packet to the transmitter for wireless transmission, a media access control (MAC) processor in data communication with the PHY processor, and a delay circuit coupled between the MAC processor and the PHY processor. The PHY processor is configured to signal the delay circuit when receiving of the first packet is completed. The MAC processor is operable to determine whether to send a response for the first packet. The MAC processor is further operable to generate the second packet responsive to determining to send a response to the first packet. The MAC processor forwards the second packet to the PHY processor and signals the delay circuit to transmit the second packet. The PHY processor waits for a signal from the delay circuit before sending the second data packet to the transmitter for wireless transmission.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a circuit for timing the transmission of a wireless signal.

FIG. 2 illustrates a representation of an example embodiment.

FIG. 3 illustrates an example of a timing diagram associated with an example embodiment.

FIG. 4 illustrates an example methodology.

DESCRIPTION OF THE EXAMPLE EMBODIMENTS

It should be appreciated that an example embodiment of the present invention as described herein makes particular reference to the IEEE 802.11 standard and utilizes terminology referenced therein. However, it should be understood that reference to the IEEE 802.11 standard and its respective terminology is not intended to limit the scope of the present invention. In this regard, the present invention is suitably applicable to a wide variety of other communication systems. Moreover, it should be appreciated that while the present invention has been described in connection with a wireless local area network (WLAN), the present invention is suitable for use in connection with other types of wireless networks, including a wireless wide area network (WWAN), a wireless metropolitan area network (WMAN) and a wireless personal area network (WPAN).

In 802.11, the MAC frame format comprises a set of fields that occur in a fixed order in all frames. Beginning on the left, the frame comprises a frame control field that is two bytes long, a duration ID field that is two bytes long, a first address field that is six bytes long, a second address field that is six bytes long, a third address field that is six bytes long, a sequence control field that is two bytes long, an optional fourth address field that is six bytes long, the frame body or payload that varies from zero to two thousand three hundred and twelve bytes in length, and the frame check sequence field. Thus, the length of an 802.11 data frame may vary from 28 to 2346 bytes in size.

Due to the variability of the size of the frame body 46 (from 0-2,312 bytes) and the requirement of 802.11 that an entity is not permitted to transmit for at least a SIFS (16 μs for 802.11a) after a packet is received, there is no way for the MAC to efficiently make the complex calculation set forth above without wasting valuable processor resources and degrading system throughput.

Referring to FIG. 1, there is illustrated an example of a circuit 10 configured for disabling a transmitter 16 from transmitting a packet for a predetermined amount of time. Circuit 10 comprises a delay circuit 12. Delay circuit 12 receives a signal (TX ENABLE) for enabling transmitter 16 to operate. Delay circuit 12 has a second input coupled to a end of packet detector circuit 14. Delay circuit 12 is responsive to end of packet detector circuit 14 signaling that the end of a packet was detected to block the TX ENABLE signal a predetermined amount of time from reaching transmitter 16. After the predetermined time period has expired, the TX ENABLE signal (DELAYED TX ENABLE) is provided to transmitter 16. Transmitter 16 is operative to begin transmission upon receipt of the DELAYED TX ENABLE signal.

In an example embodiment, circuit 10 is employed to send acknowledgement (ACK) packets to a transmission after a predetermined time in an 802.11 environment. According to the 802.11 standard, an ACK can be sent after a predetermined (e.g. SIFS) time period has expired without checking the clear channel assessment (CCA). After a packet is received, end of packet detector circuit 14 sends a signal to delay circuit 12 indicating to delay circuit 12 that a packet was just received. The acknowledgement (ACK) packet can be generated by another entity, such as a Media Access Control (MAC) processor (see e.g. MAC 54; FIG. 2) coupled to the receiver. When the ACK packet is ready for transmission, a signal (TX ENABLE) is communicated to transmitter 16. However, delay circuit 12 blocks the TX ENABLE signal from reaching transmitter 16 until a predetermined (e.g. SIFS) time period has elapsed. circuit. After the predetermined time period has elapsed, a TX ENABLE signal (DELAYED TX ENABLE) is communicated to transmitter 16. Transmitter 16 is responsive to receiving the DELAYED TX ENABLE signal to send the ACK packet.

An example embodiment described herein implements a timer tied to the PHY processor. In an example embodiment, the timer is set for the SIFS period. The timer is reset and triggered when the end of the received signal is detected. An example hardware implementation of an example embodiment is shown in FIG. 2. Typically, multiple integrated circuits are combined to implement a data communications radio 50. The primary components of the radio, from the host interface connector 52, are as follows: the media access controller 54, the baseband processor or PHY chip 56, the I/Q modulator/demodulator and synthesizer 58, the RF-to-IF converter 60, the power amplifier and detector 62, and the antennas 64A and 64B. As shown in FIG. 2, AND gate 66 is placed in series with the TX_ENABLE signal from the MAC processor to the PHY baseband processor. The output of the timer 68 is tied to the second input of the AND gate. When the timer is triggered by the PHY detecting the trailing edge of the RF packet, the second input of the AND gate is driven to a logic ‘0’, effectively disabling any transmit activity until the timer is expired. The precise implementation of the timer is not critical to this invention. For instance, the timer may be set for any pre-determined time, configured on the fly, set by the user, or by the system, etc. In the preferred embodiment, the timer should be set for the SIFS time, in this case 16 μs, or as required by the specific standard being practiced and is implemented in hardware.

A timing sequence of the present invention is shown in FIG. 3. As shown, the leading edge of the TX Gate signal does not have a fixed relationship to the RF Packet. This is permitted by the example embodiments described herein since the trailing edge of the RF packet triggers the internal TX Gate timer. When the timer expires (after 16 μs as shown), the TX Gate signal trailing edge occurs, and the ACK signal is transmitted.

Based on the example embodiment, the complex transmission time calculation in not needed, thereby eliminating the packet duration calculation and packet synchronization function such that the MAC processor is freed to perform other tasks, potentially increasing the throughput of the device. In addition, the example embodiment will also eliminate or significantly reduce the possibility of fast-turnaround protocol timing errors.

In view of the foregoing structural and functional features described above, a methodology 400 in accordance with various aspects of the present invention will be better appreciated with reference to FIG. 4. While, for purposes of simplicity of explanation, the methodology 400 of FIG. 4 is shown and described as executing serially, it is to be understood and appreciated that the present invention is not limited by the illustrated order, as some aspects could, in accordance with the present invention, occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, not all illustrated features may be required to implement a methodology in accordance with an aspect the present invention. Embodiments of the present invention are suitably adapted to implement the methodology in hardware, software, or a combination thereof.

At 402, the trailing edge of a received packet is detected. Any suitable technique for detecting the trailing edge of a packet can be employed. At 404, the transmitter is disabled. By disabled, the transmitter is inhibited from transmitting a packet, such as an ACK in response to the received packet. In an example embodiment, a transmit enable signal is blocked. At 406 a time is started. In an example embodiment, the timer is started responsive to the trailing edge of the packet being detected. At 408, the transmitter is enabled. In an example embodiment, the transmitter is enabled responsive to the time set at 406 expiring. In an example embodiment, the transmitter is enabled by allowing a previously blocked transmit enable signal to pass to the transmitter.

The present invention has been described with reference to a preferred embodiment. Obviously, modifications and alterations will occur to others upon a reading and understanding of this specification. It is intended that all such modifications and alterations be included insofar as they come within the scope of the appended claims or the equivalents thereof. 

1. An apparatus, comprising: a receiver operable to receive a wireless signal; a transmitter operable to transmit a wireless signal; a detection circuit operable to detect when receiving of the wireless signal is completed coupled to the receiver; and a delay circuit configured to receive a signal to operate the transmitter and a signal from the detection circuit indicative of when receiving of the wireless signal is completed, the delay circuit comprises an output coupled to the transmitter; wherein the delay circuit is responsive to the signal from the detection circuit to delay passing the signal to operate the transmitter to the output coupled to the transmitter a predetermined time delay after the detection circuit detects receiving of the wireless signal is completed.
 2. An apparatus according to claim 1, the delay circuit comprises a timer.
 3. An apparatus according to claim 2, the delay circuit comprises a logical gate having a first input coupled to the timer and a second input coupled to the signal to operate the transmitter.
 4. An apparatus according to claim 3, wherein the logical gate is an AND gate.
 5. An apparatus according to claim 2, wherein the timer comprises an input coupled to the signal from the detection circuit indicative of when receiving of the wireless signal is completed.
 6. An apparatus according to claim 5, wherein the timer is configured to be responsive to the signal from the detection circuit indicative of when receiving of the wireless signal is completed to reset the timer.
 7. An apparatus according to claim 6, the timer further comprises an output, wherein the timer is configured to produce a first output responsive to being reset and a second output a predetermined time after being reset.
 8. An apparatus according to claim 1, wherein the signal comprises a data packet, the detection circuit is responsive to detecting a trailing edge of the data packet to generate the signal indicative of when receiving of the wireless signal is completed.
 9. An apparatus according to claim 1, further comprising a physical layer processor coupled to the transmitter and receiver, the physical layer (PHY) processor is configured to receive the signal to operate the transmitter.
 10. An apparatus according to claim 9, further comprising a media access control (MAC) processor in data communication with the PHY processor, the MAC processor is configured to determine whether to generate a response to a signal received by the receiver and processed by the PHY processor.
 11. An apparatus according to claim 10, wherein the MAC processor determines the predetermined delay.
 12. An apparatus according to claim 11, wherein the predetermined delay is a short inter frame space.
 13. An apparatus according to claim 10, wherein the MAC processor is configured to determine whether the response is an acknowledgement (ACK) frame, the MAC processor is further configured to forward the ACK frame to the PHY processor, the PHY processor is configured to wait until the delay circuit passes the signal to operate the transmitter before transmitting the ACK.
 14. A method, comprising: receiving a signal; determining when receiving of the signal is completed; generating a response to the signal; and delaying the sending of the response a predetermined time period from when receiving of the signal is completed.
 15. A method according to claim 14, wherein the signal comprises a data packet, the determining when receiving of the signal is completed further comprises detecting a trailing edge of the data packet.
 16. A method according to claim 14, the generating a response to the signal comprises generating an acknowledgement (ACK) to the signal.
 17. A method according to claim 14, the delaying the sending of the response further comprises starting a timer.
 18. An apparatus, comprising: a wireless transmitter; a wireless receiver; a physical layer (PHY) processor coupled to the receiver and responsive to receive a first data packet from the wireless receiver, the PHY is also coupled to the transmitter and operable to send a second data packet to the transmitter for wireless transmission; a media access control (MAC) processor in data communication with the PHY processor; and a delay circuit coupled between the MAC processor and the PHY processor; wherein the PHY processor is configured to signal the delay circuit when receiving of the first packet is completed; wherein the MAC processor is operable to determine whether to send a response for the first packet; wherein the MAC processor is operable to generate the second packet responsive to determining to send a response to the first packet; wherein the MAC processor forwards the second packet to the PHY processor and signals the delay circuit to transmit the second packet; and wherein the PHY processor waits for a signal from the delay circuit before sending the second data packet to the transmitter for wireless transmission.
 19. An apparatus according to claim 18, the delay circuit comprises a timer, the timer is operable to receiving a signal from the PHY processor to output a first signal for a predetermined time period and to output a second signal after the predetermined time period expires.
 20. An apparatus according to claim 18, wherein the MAC processor controls the amount of time that the time delay circuit waits before sending the signal to the PHY processor for sending the second packet. 